1. Field of the Invention
The present invention is directed to a semiconductor device manufacturing method, and in particular to a semiconductor device manufacturing method for disposing plural semiconductor substrates having semiconductor chips one above the other, connecting semiconductor chips, each of which constitutes a different semiconductor substrate, in such a manner as to enable signal transmission, and subsequently singularizing the semiconductor chips into individual pieces.
The present invention is also directed to a semiconductor device manufacturing method for disposing in one or more layers singularized semiconductor chips on a semiconductor substrate including semiconductor chips, connecting semiconductor chips in different layers in such a manner as to enable signal transmission, and subsequently singularizing the layered semiconductor chips into individual pieces.
2. Description of the Related Art
A reduction in size, thickness and weight of semiconductor application products for use in various mobile apparatuses, such as digital cameras and portable telephones, has progressed at a rapid pace in recent years. In accordance with the trend, there are continuing demands for size reduction and density increase of semiconductor devices installed in the semiconductor application products. To meet such demands, for example, methods of manufacturing semiconductor devices having a wafer-on-wafer (hereinafter, referred to as “WOW”) configuration have been proposed. In the WOW configuration, plural semiconductor substrates (wafers) having semiconductor chips are disposed one above the other and bonded in this wafer state (see Patent Document 1, for example).
Furthermore, so-called chip-on-wafer (referred to as “COW”) technology has also been proposed, in which semiconductor chips are directly disposed on other wafer-state semiconductor chips (see Patent Document 2, for example).
The following, first, gives a brief description of a conventionally proposed method of manufacturing a semiconductor device having the WOW configuration with reference to drawings. FIGS. 1A to 1G illustrate a conventional process flow for manufacturing a WOW configuration semiconductor device.
First, in a process shown in FIG. 1A, a semiconductor substrate 110 is prepared. The semiconductor substrate 110 includes a substrate body 120, a semiconductor integrated circuit 130 and via holes 140 which are filled with metal. The semiconductor integrated circuit 130 is formed on the substrate body 120, and the via holes 140 filled with metal are formed in the substrate body 120 and the semiconductor integrated circuit 130. When the semiconductor substrate 110 is prepared, the via holes 140 may be formed in the substrate body 120 prior to the formation of the semiconductor integrated circuit 130, or the semiconductor integrated circuit 130 may be formed on the substrate body 120 prior to the formation of the via holes 140. Note that since the substrate body 120 is reduced in thickness in a process to be described below, the via holes 140 do not have to penetrate the substrate body 120 at this point.
Next in a process shown in FIG. 1B, a support 300 is bonded to the semiconductor substrate 110 on the semiconductor integrated circuit 130 side. A glass substrate, for example, may be used for the support 300. Subsequently, in a process shown in FIG. 10, the substrate body 120 is reduced in thickness. The thickness reduction is achieved by, for example, polishing a surface of the substrate body 120, on which surface the semiconductor integrated circuit 130 is not formed. The semiconductor substrate 110 and the substrate body 120 after the thickness reduction are referred to as the semiconductor substrate 110a and the substrate body 120a, respectively. The support 300 has a function of supporting the semiconductor substrate 110a having reduced rigidity after the thickness reduction. Then, bumps (not shown) are formed on the via holes 140 exposed from the surface on which the thickness reduction has been performed. Note that the bumps (not shown) may be formed via electrode pads (not shown).
Next in a process shown in FIG. 10, a semiconductor substrate 210 is prepared. The semiconductor substrate 210 includes a substrate body 220, a semiconductor integrated circuit 230 and via holes 240 which are filled with metal. The semiconductor integrated circuit 230 is formed on the substrate body 220, and the via holes 240 filled with metal are formed in the substrate body 220 and the semiconductor integrated circuit 230. Bumps (not shown) are formed on the via holes 240 exposed from the surface of the semiconductor substrate 210 on the semiconductor integrated circuit 230 side. Note that the bumps (not shown) may be formed via electrode pads (not shown). Then, the semiconductor substrate 210 is bonded to the semiconductor substrate 110a in such a manner that the semiconductor integrated circuit 230 of the semiconductor substrate 210 opposes the substrate body 120a of the semiconductor substrate 110a. Note that the via holes 240 are formed in advance at positions corresponding to the via holes 140, and each set of the corresponding via holes 240 and 140 are electrically connected via a bump.
Next in a process shown in FIG. 1E, the substrate body 220 is reduced in thickness, in the same manner as in the process of FIG. 10. The semiconductor substrate 210 and the substrate body 220 after the thickness reduction are referred to as the semiconductor substrate 210a and the substrate body 220a, respectively. Then, bumps (not shown) are formed on the via holes 240 exposed from the surface on which the thickness reduction has been performed. Note that the bumps (not shown) may be formed via electrode pads (not shown).
Next in a process shown in FIG. 1F, by repeating the same processes of FIGS. 1D and 1E, semiconductor substrates 310a and 410a are disposed one above the other at the bottom of the substrate body 220a of the semiconductor substrate 210a. Then in a process shown in FIG. 1G, the support 300 of FIG. 1F is removed. Herewith, a semiconductor device 100 is completed. In this manner, the WOW-configuration semiconductor device 100 is manufactured in which the semiconductor substrates 110a, 210a, 310a and 410a with reduced thicknesses are bonded to one another in the semiconductor substrate (wafer) state.
FIGS. 2A to 2C illustrate another conventional process flow for manufacturing a WOW configuration semiconductor device. In FIGS. 2A to 2C, the same reference numerals are given to the components which are common in FIGS. 1A to 1G, and their explanations may be omitted. First, in a process shown in FIG. 2A, semiconductor substrates 510 and 610 are prepared. The semiconductor substrate 510 includes a substrate body 520 and a semiconductor integrated circuit 530. The semiconductor integrated circuit 530 is formed on the substrate body 520. The semiconductor substrate 610 includes a substrate body 620 and a semiconductor integrated circuit 630. The semiconductor integrated circuit 630 is formed on the substrate body 620. Then, the semiconductor substrate 610 is bonded to the semiconductor substrate 510 in such a manner that the semiconductor integrated circuit 630 of the semiconductor substrate 610 opposes the semiconductor integrated circuit 530 of the semiconductor substrate 510.
Next in a process shown in FIG. 2B, the substrate body 620 is reduced in thickness. The thickness reduction is achieved by, for example, polishing a surface of the substrate body 620, on which surface the semiconductor integrated circuit 630 is not formed. The semiconductor substrate 610 and the substrate body 620 after the thickness reduction are referred to as the semiconductor substrate 610a and the substrate body 620a, respectively. Subsequently, in a process shown in FIG. 2C, via holes 640 filled with metal are formed in such a manner to penetrate the substrate body 620a and connect the semiconductor integrated circuit 530 and the semiconductor integrated circuit 630. In this manner, a WOW-configuration semiconductor device 500 is manufactured in which the semiconductor substrate 510 and the semiconductor substrate 610a with a reduced thickness are bonded to one another in the semiconductor substrate (wafer) state.    Patent Document 1: Japanese Laid-open Patent Application Publication No. 2008-153499    Patent Document 2: Japanese Laid-open Patent Application Publication No. 2010-278279
However, the semiconductor device manufacturing method shown in FIGS. 1A to 1G requires, when two semiconductor substrates are connected, a process of forming bumps on the via holes exposed from both semiconductor substrates, thus leaving the problems of low productivity and an increase in the cost of manufacturing the semiconductor device.
According to the semiconductor device manufacturing method shown in FIGS. 2A to 2C, since the semiconductor substrates are bonded in such a manner that the surfaces on which the semiconductor integrated circuits have been formed oppose each other, three or more semiconductor substrates cannot be disposed one above the other by simply repeating the same processes. That is, a special process is required to dispose three or more semiconductor substrates one above the other, which results in low productivity and an increase in the cost of manufacturing the semiconductor device.
Also, according to either of the semiconductor device manufacturing methods shown in FIGS. 1A to 1G and FIGS. 2A to 2C, in the case of forming deep via holes, it takes a long time to perform the hole-formation of the via holes and the metal filling process and also the number of materials required for the processes increases, which leads to an increase in the cost of manufacturing the semiconductor device.
Furthermore, according to either of the semiconductor device manufacturing methods shown in FIGS. 1A to 1G and FIGS. 2A to 2C, in the case of forming the via holes by dry etching or the like, the depths of the via holes change according to the size and density of the via holes, which leads to the variation in the diameter of the end portions of the via holes. As a result, the diameter of the via holes exposed when the semiconductor substrate is reduced to a desired thickness varies, which in turn results in the variation in the resistance of the electrical connections, leaving the problem of decreased reliability of the semiconductor device.
As for conventional COW technology, the following methods have been used: a method of burying connecting holes (TSVs) having a large aspect ratio and forming bumps or metal protrusions to connect semiconductor chips to each other; and a method of stacking together semiconductor chips with their device-side surfaces (i.e., surfaces on each of which a semiconductor integrated circuit is formed) face-to-face, performing thickness reduction and connecting the semiconductor chips by connecting holes (TSVs).
The former method requires, when the semiconductor chips are connected, a process of forming bumps or metal protrusions on via holes exposed from the semiconductor chips, thus leaving the problems of low productivity and an increase in the cost of manufacturing the semiconductor device. According to the latter method, since the semiconductor chips are connected to one another with their device-side surfaces opposing each other, it is necessary to have a preformed wiring design and there is therefore little flexibility in the connection wiring. In addition, three or more semiconductor chips cannot be disposed one above the other by simply repeating the same processes. That is, a special process is required to dispose three or more semiconductor chips one above the other, which results in low productivity and an increase in the cost of manufacturing the semiconductor device.
Also, according to either of the methods above, in the case of forming deep via holes, it takes a long time to perform the hole-formation of the via holes and the metal layer forming process and also the number of materials required for the processes increases, which leads to an increase in the cost of manufacturing the semiconductor device.
Furthermore, according to either of the methods above, in the case of forming the via holes by dry etching or the like, the depths of the via holes change according to the size and density of the via holes, which leads to the variation in the diameter of the end portions of the via holes. As a result, the diameter of the via holes exposed when the semiconductor substrate is reduced to a desired thickness varies, which in turn results in the variation in the resistance of the electrical connections, leaving the problem of decreased reliability of the semiconductor device.